(a) Field of the Invention
The present invention relates to a thin film transistor array panel and a method thereof, and in particular, to a polysilicon thin film transistor array panel.
(b) Description of the Related Art
Thin film transistors (TFT) are used for driving pixels in a liquid crystal display (LCD) and electro luminescence (EL) display. A panel including the TFTs also includes a plurality of gate lines transmitting scanning signals for turning on and off the TFTs and a plurality of data lines transmitting data signals for the display of the pixels.
The TFTs include polysilicon or amorphous silicon as active layers. When the display panel includes polysilicon TFTs for switching the data signals to be supplied to the pixels, driving circuits for generating the scanning signals and the data signals can be also formed on the display panel along with the TFTs for the pixels such that cost and complexity for mounting driving chips are reduced.
The driving circuits include a plurality of driving TFTs, which have the same layered structure as the TFTs for the pixels (referred to as “pixel TFTs” hereinafter). The driving circuits typical include both N type TFTs and P type TFTs.
The TFTs include polysilicon members doped with N type or P type impurity. In order to both the N type and the P type polysilicon members, ion implantation is performed twice usually using the gate lines as an implantation mask. The gate lines exposed to the ionic impurity are charged to yield electrostatic discharge (ESD) damages. The ESD damages are generated between adjacent gate members and they become severe when the sizes of the gate members are different since the voltage difference become larger.
The large current due to the ESD makes damage on a gate insulating layer located between the gate lines and the silicon active layers and it melts the silicon layers to be agglomerated or evaporated.
In order to ESD protection, protection diodes are formed in the manufacturing process. However, since the protection diodes are activated after forming the data lines, there is no ESD protection mechanism before the formation of the data lines.
Although a technique for minimizing the difference in the areas between adjacent gate members is suggested, there is difficulty in designing the gate members to fixed areas. In addition, this technique is somewhat effective in reducing defect ratio, but it is insufficient for preventing the ESD damage due the difference in impurity doping amount between the gate members.